(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to fabricate image sensing devices.
(2) Description of Prior Art
Active pixel sensor cells are usually comprised of active image sensing elements, such as photodiodes, in addition to active transistor structures, such as a reset transistor, as well as transfer transistor structures. The active pixel sensor cell is basically used to collect light energy, and then converted to an electrical signal, enabling read out to occur. Enhancements such as the use of pinned photodiodes, as the image sensing elements of the active pixel sensor cells, have allowed unwanted dark current phenomena to be reduced, resulting in increased signal to noise, (S/N) ratios to be realized, when compared to counterpart, non-pinned photodiode structures. The active pixel sensor cell is fabricated simultaneously with other complimentary metal oxide semiconductor, (CMOS), devices, used in peripheral CMOS circuits, sharing many process steps and sequences.
This invention will describe a active pixel sensor cell, formed using a pinned photodiode element, and featuring a readout region formed within the photodiode region. This concept eliminates the need for the transfer gate transistor structure, improving cell density. The P+ element of the pinned photodiode structure, can be formed simultaneously with P+ source/drain regions, used in the logic regions of CMOS, control circuits, or CMOS processing circuits, of the active pixel sensor cell. Prior art, such as Lee et al, in U.S. Pat. No. 5,625,210, as well as Chen, in U.S. Pat. No. 5,880,495, describe active pixel sensor cells, however without the concept of placing the readout region, in the photodiode area, eliminating the use of the transfer gate transistor.
It is an object of this invention to fabricate an active pixel sensor cell using a pinned photodiode element.
It is another object of this invention to form the readout region, for an active device sensor, in the pinned photodiode region.
It is still another object of this invention to eliminate the transfer gate transistor structure, from the active pixel sensor cell, made possible by the placement of an N+ readout region, within the photodiode region.
In accordance with the present invention the fabrication of, and the structure of, an active pixel sensor cell, featuring a pinned photodiode element, and featuring the formation of, and the placement of, a readout region in the photodiode region, is described. A gate structure, of a reset transistor, comprised of a polysilicon gate structure on an underlying gate insulator layer, is formed on a first region of a P type, semiconductor substrate. After formation of insulator spacers, on the sides of the gate structure of the reset transistor, heavily doped, N+ source/drain regions, are formed adjacent to the gate structure, in areas of the first region of the P type semiconductor region, not covered by the gate structure. In addition a heavily doped, N+ region, is also formed in a first portion, of the second region of the P type semiconductor substrate, to be used as a readout region for an active pixel sensor. A deep N type well is next formed in the entire second region of the P type semiconductor substrate, with the shallower N+ readout region, occupying a first portion of the deep N type well region, which in turn is located adjacent to, and butted to, the heavily doped, N+ source/drain region, of the reset transistor. Heavily doped P+ regions are next formed in second portions of the N type well region, resulting in the pinned photodiode, comprised of a shallow P+ region, in the N type well region, with the pinned photodiode residing in the P well, or in the P type semiconductor substrate. The N + readout region, in the N type well region, is surrounded by the P+ region. After formation of a contact hole opening, in an insulator layer, exposing a portion of the top surface of the N+ readout region, a metal structure is formed, in the contact hole opening, for communication with the N+ readout region.
An additional iteration of this invention is to form the deep N type well, in the second region of the P type semiconductor substrate, prior to formation of the gate structure located in the first region of the P type semiconductor substrate.